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| Ordering number : ENN7350 CMOS IC LC78684E MP3 Decoder for Compact Disc Players Overview The LC78684E integrates, on a single chip, CD-ROM signal-processing functions, MP3 signal-processing functions, and CD-DA shockproof signal-processing functions. The LC78684E achieves significant power savings by implementing signal-processing functions using hardwired structures. A CD player that supports playback of MPEG audio (MP3) recorded on CD media as well as CD-DA shockproof playback can be implemented by combining this IC with a CD DSP, DRAM, and audio D/A converter, and other circuits. CD-ROM Decoding Functions Supports CD-ROM modes 1 and 2 (forms 1 and 2) Faithfully reproduces data stored on CD-ROM discs using CD-ROM error correction functions. Header and sector management Supports playback speeds up to 4x. In addition to data buffering also supports C2 error flag buffering. Provides external serial output of decoded CD-ROM data. CD-DA Playback Functions (Shockproof support) Shockproof operation for about 180 seconds (compressed mode) when 64M DRAM is used. Shockproof function supports compressed, uncompressed, and data through modes. VCEC (variable speed) supports up to 4x-speed playback. Audio Signal Processing Serial audio signal output using LRCK, BCK, and DATA signals. (IS format, either 16-bit or 20-bit precision PCM output, data-slot supports 16-bit, 24-bit, and 32-bit modes) Digital bass boost function (4 modes), attenuator function, and muting ( , 12 dB) Provides a base clock (384 fs) output pin for use with external digital filters and D/A converters. DRAM Interface Supports the use of from 1M to 64M of external DRAM (EDO, 2CAS, 16-bit data bus memory) Supports allocation of a user area in DRAM during CD-ROM (MP3) playback. Continued on next page. Features MP3 Decoding Functions (MPEG audio standard [ISO/IEC 11172-3] layer 3) Decodes to a digital audio signal MP3 data decoded by the CD-ROM decoder and outputs that audio signal. Supports all bit rates, including variable bit rate operation. Supports the following sampling rates. MPEG1 (Fs = 32 K, 44.1 K, 48 K) MPEG2 (Fs = 16 K, 22.05 K, 24 K) MPEG2.5 (Fs = 8 K, 11.025 K, 12 K) Can read out the MPEG header and ancillary data. Automatically mutes the signal on CRC errors using an MP3 CRC check function. External MPEG serial data input function supports memory card playback. Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. 20703RM(OT) No.7350-1/21 LC78684E Continued from preceding page. Package and Power Supply Voltage Specifications Package: Sanyo QFP80 (14 x 14) (unit: mm) Supply voltage Internal power supply: 1.8 V (typical) I/O power supply: 3.3 V (typical) Analog system power supply: 3.3 V (typical) Package Dimensions Unit: mm 3255-QFP80 (14 14) [LC78684E] 17.2 60 61 41 40 0.8 14.0 80 1 (0.83) 3.0max (2.7) 21 0.65 0.25 20 0.15 0.1 15.6 14.0 17.2 MPEG Layer3 audio coding technology licensed from Fraunhofer IIS and THOMSON multimedia SANYO: SFP80 No.7350-2/21 LC78684E Block Diagram MDATA[15:0] MADRS[12:0] INTB CMDOUT CMDIN CE CL RASB CASUB CASLB OEB WEB CKIN VPRFR VCOC VPDO CKOUT System clockgenerator VCO PLL CPU-I/F DRAM-I/F WOK CNTOK OVF CD-DA shockproof (Compressed or uncompressed) CDROM decoder Data-I/F STREQ STCK STDAT CRCF LRSY DATACK DATAIN C2FIN SFSY PW SBSY SBCK MP3 decoder FSYNC M U X RESB Audio I/F ADLRCK ADBCK ADDATA No. 7350-3/21 LC78684E Pin Assignment DATACK CMDOUT DATAIN CNTOK STREQ CMDIN FSYNC DVDD6 STDAT RESB CRCF WOK INTB OVF 80 79 78 77 76 75 74 73 72 71 70 69 VSS CE CL 68 67 66 65 64 63 62 LRSY 1 ADDATA 2 ADBCK 3 ADLRCK 4 C2FIN 5 TEST1 6 CKIN 7 VSS 8 CKOUT 9 TEST2 10 DVDD1 11 PW 12 SBSY 13 SFSY 14 SBCK 15 AVDD 16 VPRFR 17 VCOC 18 VPDO 19 AVSS 20 DVDD2 21 VSS 22 MDATA0 23 MDATA1 24 MDATA2 25 MDATA3 26 MDATA4 27 MDATA5 28 MDATA6 29 MDATA7 30 DVDD3 31 VSS 32 MDATA8 33 MDATA9 34 MDATA10 35 MDATA11 36 MDATA12 37 MDATA13 38 MDATA14 39 MDATA15 40 61 DVDD5 STCK VSS 60 59 58 57 56 55 54 53 MADRS0 MADRS1 MADRS2 MADRS3 MADRS4 MADRS5 MADRS6 MADRS7 VSS DVDD4 MADRS8 MADRS9 MADRS10 MADRS11 MADRS12 OEB CASUB CASLB WEB RASB LC78684 (Top view) 52 51 50 49 48 47 46 45 44 43 42 41 No.7350-4/21 LC78684E Pin Functions Absolute Maximum Ratings at VSS Parameter Maximum supply voltage Input voltage Output voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD max VIN VOUT Pdmax Topr Tstg 0 V, AVSS 0V Conditions Ratings 0.3 to VSS 4.0 0.3 to VDD1 0.3 0.3 to VDD1 0.3 400 30 to 75 40 to 125 Unit V V V mW C C Allowable Operating Ranges at Ta Parameter Supply voltage Symbol VDD1 VDD2 30 to 75 C, VSS Pin name DVDD1, DVDD3, DVDD4, DVDD6, AVDD DVDD2, DVDD5 MDATA0 to 15, LRSY, DATAIN, DATACK, C2FIN, PW, SBSY, SFSY, STREQ, STCK, STDAT, WOK, CKIN, CE, CL, CMDIN, RESB MDATA0 to 15, LRSY, DATAIN, DATACK, C2FIN, PW, SBSY, SFSY, STREQ, STCK, STDAT, WOK, CKIN, CE, CL, CMDIN, RESB, TEST1, TEST2 CKIN 0 V, AVSS 0V min 3.0 1.62 Ratings typ 3.3 1.8 max 3.6 1.98 Unit V V Conditions High-level input voltage VIH 0.8 VDD1 VDD1 V Low-level input voltage VIL 0 0.2 VDD1 V Operating frequency range Fop 16.9344 MHz No.7350-5/21 LC78684E 30 to Electrical Characteristics at Ta AVSS 0 V Parameter Symbol IDD (1) Current drain IDD (2) DVDD2, DVDD5 MDATA0 to 15, LRSY, DATAIN, DATACK, C2FIN, PW, SBSY, SFSY, STREQ, STCK, STDAT, WOK, CKIN, CE, CL, CMDIN, RESB MDATA0 to 15, LRSY, DATAIN, DATACK, C2FIN, PW, SBSY, SFSY, STREQ, STCK, STDAT, WOK, CKIN, CE, CL, CMDIN, RESB, TEST1, TES2 MDATA0 to 15, STREQ, STCK, STDAT, MADRS0 to 12, RASB, CASUB, CASLB, OEB, WEB SBCK, ADDATA, ADLRCK, ADBCK, INTB, FSYNC, CRCF, CNTOK, OVF CKOUT VPDO MDATA0 to 15 STREQ, STCK, STDAT, MADRS0 to 12, RASB, CASUB, CASLB, OEB, WEB SBCK, ADDATA, ADLRCK, ADBCK, INTB, FSYNC, CRCF, CNTOK, OVF, CMDOUT CKOUT VPDO MDATA0 to 15, STREQ, STCK, STDAT, CMDOUT MDATA0 to 15, STREQ, STCK, STDAT, CMDOUT 75 C, VDD1 3.0V to 3.6 V, VDD2 1.62 V to 1.98 V, VSS Ratings typ 10.0 4.5 0 V, Pin name DVDD1, DVDD3, DVDD4, DVDD6, AVDD Conditions VDD1 3.0 to 3.6 V VDD2 1.62 to 1.98 V min max 20.0 10.0 Unit mA mA High-level input current IIH VIN VDD1 10 A Low-level input current IIL VIN 0V 10 A VOH (1) High-level output voltage IOH 2 mA VDD1 0.6 V VOH (2) VOH (3) IOH 4 mA IOH 0.2 mA VDD1 0.6 VDD1 0.6 V * VOL (1) Low-level output voltage IOL 2 mA 0.4 V VOL (2) VOL (3) IOL 4 mA IOL 0.2 mA VDD1 0.4 0.4 V * IOFF (1) Output off leakage current IOFF (2) VOUT 10 A VOUT 0V 10 A No.7350-6/21 LC78684E Microcontroller Interface Microcontroller Interface Timing Write Cycle T1 CE CL T5 CMDIN T6 T7 T4 T2 T3 Read Cycle T1 CE CL T5 CMDOUT T9 T8 T10 T4 T2 T3 Parameter CE/CL setup time CE/CL hold time Command wait time CL H-level pulse width CL L-level pulse width Data/CL setup time Data/CL hold time Data-read access time Data-read turn-on time Data-read turn-off time : Pull-up resistor 1 K , Output load 30 pF Symbol T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 min 500 250 1000 250 250 150 150 0 0 0 Ratings typ max Unit ns ns ns ns ns ns ns ns ns ns 240 150 240 No.7350-7/21 LC78684E Command Input/Data Output Interface Input commands (i.e. write data to the LC78684E) in the order data first and then address. The data and address are LSB first. Output data is output (i.e. read data from the LC78684E) by first issuing a read mode setup command and then performing read access operations. Data write CE CL CMDIN LSB MSB LSB MSB Data CMDOUT Address High (Held high with an external pull-up resistor) Data read Data is read by first writing the register address to be read to location $61h and then setting up read mode by setting CE low temporarily. When CE is set high again, and the CL signal is issued, the contents of the specified register are output from CMDOUT, LSB first. The microcontroller must perform a read access if it sets up read mode. Read mode setup command CE CL Read access CMDIN LSB MSB LSB MSB Register address Read code (61h) CMDOUT High (Held high with an external pull-up resistor) LSB MSB No.7350-8/21 LC78684E Memory Interface Memory Interface Timing Read Cycle T1 RASB T2 CASUB/LB T4 T8 T9 Column T5 T3 T6 MADRS[12:0] T7 Row Column Column WEB T10 T12 T13 Read data T11 OEB Read data MDATA[15:0] Read data Write Cycle T1 RASB T2 CASUB/LB T4 T8 T9 T5 T3 T6 MADRS[12:0] T7 Row Column T14 Column Column T15 WEB OEB T16 T18 T19 Write data Write data Write data T17 MDATA[15:0] No.7350-9/21 LC78684E Refresh Cycle (CAS before RAS) T20 T21 RASB T22 T23 T24 CASUB/LB T17 MDATA[15:0] Parameter RASB width high RASB CASB delay CASB RASB delay CASB width low CASB width high Row address setup time Row address hold time Column address setup time Column address hold time OEB ready time OEB hold time Read data setup time Read data hold time WEB ready time WEB hold time Write data turn on time Write data turn off time Write data setup time Write data hold time Refresh cycle RASB low width (refresh) RASB CASB delay (refresh) CASB setup time (refresh) CASB hold time (refresh) Symbol T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 min 100 80 40 40 40 15 40 15 40 30 10 30 0 30 40 Ratings typ max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 60 80 15 40 300 200 50 40 100 : These values apply when the frequency of the clock input to the CKIN pin is 16.9344 MHz. No.7350-10/21 LC78684E CD DSP Interface CD DSP Interface Timing LRSY T2 T1h Fbck DATACK DATAIN T4 C2FIN T5 T3 T1l Parameter DATACK frequency DATACK H-level pulse width DATACK L-level pulse width LRSY setup time LRSY hold time DATA, C2FIN setup time DATA, C2FIN hold time Symbol Fbck T1h T1l T2 T3 T4 T5 min 30 30 30 30 30 25 Ratings typ max 14.5 Unit MHz ns ns ns ns ns ns : The figure above shows the timings when DATACK rising edge latch is used. If DATACLK falling edge latch is used, the timings are the same as those for the corresponding setup and hold signal. No.7350-11/21 LC78684E Subcode Interface Timing Subcode Frame SF97 SF0 SF1 SF2 SF3 SBSY SFSY PW SBCK Tssd T1h SBCK Fsbck PW T2 T3 T1l Parameter SFSY SBCK delay time SBCK frequency SBCK H-level pulse width SBCK L-level pulse width PW setup time PW hold time Symbol Tssd Fsbck T1h T1l T2 T3 min 235 450 450 50 0 Ratings typ 1.0584 max 7150 Unit ns MHz ns ns ns ns : These values apply when the frequency of the clock input to the CKIN pin is 16.9344 MHz. No.7350-12/21 LC78684E Audio Output Interface Audio Output Interface Timing T1 ADLRCK ADBCK T2 ADDATA CKOUT Fck T3 The figure above applies when the 48-bit slot is used for the audio data output slot. Parameter CKOUT ADLRCK delay time CKOUT ADBCK delay time CKOUT ADDATA delay time CKOUT frequency : These values apply during MPEG1 data playback (fs Symbol T1 T2 T3 Fck fs Ratings typ Unit ns ns ns MHz min 0 0 0 max 35 35 35 16.9344 384) 44.1 kHz) when the PLL circuit is locked normally. These values depend on the playback sampling frequency (fs). (CKOUT frequency Supplement: Output Timing for Full Through Mode Playback LRSY DATACK DATAIN T5 ADLRCK ADBCK ADDATA CKIN T6 CKOUT : Full through mode is the state where the THROUGH bit (60h: bit 6) is set to 1. Ratings typ Parameter INPUT OUTPUT delay time CKIN CKOUT delay time Symbol T5 T6 min 0 0 max 35 35 Unit ns ns : These values apply when the signal input to the CKIN pin is directly output from the CKOUT pin. No.7350-13/21 LC78684E Serial Data I/O Interface DRAM Serial Data Output Timing T5 T3 T4 T6 STREQ STCK STDAT CRCF Fsck STCK STDAT T1 T2 T7 : Performing a serial data output operation requires that a command to transfer data from DRAM be issued. If this command has not been issued, the STCK and STDAT pins will not output the clock and data signals, even if the STREQ goes high. Ratings typ 4.2336 Parameter Transfer clock frequency STDAT/STCK setup time STDAT/STCK hold time Data (1byte) transfer time Data transfer wait time Data transfer start time Data transfer stop time Enable flag turn off time Symbol Fsck T1 T2 T3 T4 T5 T6 T7 min 30 30 max Unit MHz ns ns s s s s ns 1.89 1.89 1.89 0 210 15.2 15.2 270 236.2 Notes: The typical values shown apply when the frequency of the clock input to the CKIN pin is 16.9344 MHz. The fsck clock frequency can also be set to 2.1168 or 1.0584 MHz (typical). The values of T3 to T7 will be, in that case, 2 or 4 times the values shown. When the STREQ pin is in input mode, the WOK, OVF, and CNTOK pins can be used instead of the STREQ, STCK, and SDAT pins. The timing specifications in this case are the same as those shown above. No.7350-14/21 LC78684E MP3 Serial Data Input Timing STREQ (*Output from the LC78684E) STCK STDAT Fsck STCK T1l T1h STDAT T2 T3 Performing a serial data input operation requires that a serial input command be issued. If this command has not been issued, the MP3 decoder will not operate, even if clock and data signals are applied to the STCK and STDAT pins. Ratings typ Parameter Transfer clock frequency STCK H-level pulse width STCK L-level pulse width STDAT/STCK setup time STDAT/STCK hold time Symbol Fsck T1h T1l T2 T3 min 45 45 30 30 max 9.216 Unit MHz ns ns ns ns : The table below lists the maximum frequencies for the transfer clock during serial input operations. Maximum serial transfer clock frequency (MHz) 9.216 8.4672 6.144 4.608 4.2336 3.072 MODE MPEG1 Fs (KHz) 48 44.1 32 24 (12) 22.05 (11.025) 16 (8) MPEG2 (MPEG2.5) The transfer clock rate must be set to a speed less than or equal to the speed shown in the table so that the MP3 decoding processing will complete in time. Note that the table above applies when MP3DSET (register 41h, bit 0) is set to 1 (high-speed transfer mode). The timings shown below apply when MP3DSET is set to 0 (low-speed transfer mode). Parameter Transfer clock frequency STCK H-level pulse width STCK L-level pulse width STDAT / STCK setup time STDAT / STCK hold time Symbol Fsck T1h T1l T2 T3 Ratings typ Unit MHz ns ns ns ns min 150 150 125 125 max 3.072 No.7350-15/21 LC78684E System Clock Input Fck CKIN pin input signal Twh Twl Parameter CKIN Input frequency CKIN H-Level pulse width CKIN L-Level pulse width Symbol Fck Twh Twl min 20 20 Ratings typ 16.9344 max 18.0 Unit MHz ns ns System Reset Input RESB pin input signal Trst Parameter System reset pulse width Symbol Trst min 1 Ratings typ max Unit s : A system reset must be performed immediately after power is first applied. Design the system so that no noise appears on the reset line. No.7350-16/21 LC78684E Pin Functions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Pin Name LRSY ADDATA ADBCK ADLRCK C2FIN TEST1 CKIN VSS CKOUT TEST2 DVDD1 PW SBSY SFSY SBCK AVDD VPRFR VCOC VPDO AVSS DVDD2 VSS MDATA0 MDATA1 MDATA2 MDATA3 MDATA4 MDATA5 MDATA6 MDATA7 DVDD3 VSS MDATA8 MDATA9 MDATA10 MDATA11 MDATA12 MDATA13 MDATA14 MDATA15 RASB WEB CASLB CASUB OEB MADRS12 MADRS11 MADRS10 MADRS9 MADRS8 I/O I O O O I I I O I I I I O CD IF Audio interface CD IF Test CLOCK Power supply CLOCK Test Power supply Subcode interface Power supply I O PLL Block Function CD left/right clock input Audio data output Audio bit clock output Audio left/right clock output CD C2 error flag input Test input 1 (This pin must be connected to ground during normal operation.) System clock input (16.9344 MHz) Ground External digital filter and D/A converter clock (384 fs) output Test input 2 (This pin must be connected to ground during normal operation.) Digital I/O system power supply CD subcode data serial input CD subcode block sync signal input CD subcode frame sync signal input CD subcode transfer serial clock output Analog system (PLL) power supply VCO oscillator range setting VCO control voltage input VCO charge pump output Analog system ground Internal logic system power supply GND DRAM data bus 0 DRAM data bus 1 DRAM data bus 2 DRAM data bus 3 DRAM data bus 4 DRAM data bus 5 DRAM data bus 6 DRAM data bus 7 Digital I/O system power supply GND DRAM data bus 8 DRAM data bus 9 DRAM data bus 10 DRAM data bus 11 DRAM data bus 12 DRAM data bus 13 DRAM data bus 14 DRAM data bus 15 RAS output (active low) WE output (active low) CAS output (lower byte, active low) CAS output (upper byte, active low) OE output (active low) DRAM address output 12 DRAM address output 11 DRAM address output 10 DRAM address output 9 DRAM address output 8 Power supply I/O I/O I/O I/O I/O I/O I/O I/O Memory interface Power supply I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O O Memory interface Continued on next page. No.7350-17/21 LC78684E Continued from preceding page. Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Pin Name DVDD4 VSS MADRS7 MADRS6 MADRS5 MADRS4 MADRS3 MADRS2 MADRS1 MADRS0 DVDD5 VSS STREQ STCK STDAT FSYNC CRCF DVDD6 VSS WOK CNTOK OVF CMDOUT CMDIN CL CE INTB RESB DATAIN DATACK I O O O I I I O I I I CD-DA shockproof and MP3 I/O I/O Block Power supply O O O O O O O O Function Digital I/O system power supply Ground DRAM address output 7 DRAM address output 6 DRAM address output 5 DRAM address output 4 DRAM address output 3 DRAM address output 2 DRAM address output 1 DRAM address output 0 Internal logic system power supply GND MP3 data request flag output (active high) /DRAM data request flag input (CD-ROM mode, active high) MP3 data transfer clock input /DRAM data transfer clock output MP3 serial data input /DRAM serial data output MP3 frame sync signal (active high) /Data continuity point detection complete flag (CD-DA mode, active high) CRC check result output (CD-ROM data/CD-DA subcode data) /DRAM data output enable signal output (active high) Digital I/O system power supply GND DRAM write enable input (CD-DA mode, active high) /DRAM data request flag input Data continuity point detection complete flag (CD-DA mode, active high) /SYNC error monitor flag (MP3 mode, active high)/DRAM serial data output DRAM write interrupt flag (CD-DA mode, active high) /Emphasis output flag (CD-DA and MP3 modes, active high) /DRAM data transfer clock output Serial command data output (n-channel open-drain output) Serial command data input Serial command clock input Command enable input (active high) Interrupt signal output (active low) /DRAM write interrupt flag (CD-DA mode, active high) System reset (active low) Serial CD data input CD bit clock input Memory interface Power supply I/O I/O I/O O O MP3-dec CD monitor Power supply MP3 stream I/O Microcontroller interface CD IF Notes: 1. Notes on unused pins. Unused input pins must be connected to the ground level (0 V). Unused output pins must be left open. Do not connect anything to these pins. Unused I/O pins may either be connected to the ground level (0 V) or set to output mode and left open. 2. The corresponding power supply levels must be provided to all of the DVDD1, DVDD3, DVDD4, DVDD6, and AVDD pins. The corresponding power supply level must also be provided to DVDD2 and DVDD5. (See the Allowable Operating Ranges specifications for the supply levels.) 3. The TEST1 and TEST2 input pins must be connected to ground (0 V). 4. The I/O pins (MDAT0:15, STREQ, STCK, and STDAT) go to input mode after a reset. 5. After first applying the power supply levels, the RESB pin must be held low for at least 1 s. 6. A 16.9344 MHz clock signal must be supplied to the CKIN pin by the CD DSP. The LC78684E does not support the implementation of an oscillator circuit using an oscillator element. No.7350-18/21 LC78684E Sample Application Circuit 1.8 V 3.3 V To DRAM To Microcontroller GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 LRSY ADDATA ADBCK ADLRCK C2FIN VSS CKIN VSS CKOUT VSS DVDD1 PW SBSY SFSY SBCK AVDD VPRFR VCOC VPDO AVSS 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 MADRS0 MADRS1 MADRS2 MADRS3 MADRS4 MADRS5 MADRS6 MADRS7 VSS DVDD4 MADRS8 MADRS9 MADRS10 MADRS11 MADRS12 OEB CASUB CASLB WEB RASB 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 DVDD5 VSS STREQ STDAT STDAT FSYNC CRCF DVDD6 VSS WOK CNTOK OVF CMDOUT CMDIN CL CE INTB RESB DATAIN DATACK LC78684E MDATA15 MDATA14 MDATA13 MDATA12 MDATA11 MDATA10 MDATA9 MDATA8 VSS DVDD3 MDATA7 MDATA6 MDATA5 MDATA4 MDATA3 MDATA2 MDATA1 MDATA0 VSS DVDD2 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 To CD-DSP : The CKOUT, ADLRCK, ADBCK, and ADDATA pins must be connected to a CD DSP that supports external D/A converter input. An external D/A converter is required if the CD DSP does not provide that functionality. No.7350-19/21 LC78684E Application Design Notes While it goes without saying that strictly observing the absolute maximum ratings and allowable operating ranges (recommended operation conditions) stipulated for this IC is necessary to achieve reliability of the overall system, it is also necessary to take adequate care with respect to the mounting conditions and the operating environment, including the ambient temperature and the possibility of electrostatic discharges (ESD). This section presents notes on aspects of design and mounting that require special attention. Handling Unused Pins If this IC is operated with unused input pins left open, certain internal circuit operations may become unstable. Unused pins that are mentioned in the IC documentation must be handled as specified. Also, do not allow output pins to come in contact with any circuit lines, including power supply lines, ground lines, or other outputs. Latchup Prevention The voltages stipulated in the IC specifications must be provided to the corresponding power supply pins. When the same voltage is stipulated for multiple pins, those pins all must be connected to the same potential. Do not set I/O voltage levels to be either higher than the peripheral 3 V system block voltage, or lower than the ground level. This relationship must also be maintained during the power-on sequence. Do not apply overvoltages or abnormal noise to this IC. While in general, latchup is prevented by holding unused input pins at either the VDD or VSS potential, input pins to this IC must be handled as described in the pin descriptions. Do not short the outputs. Interface Incorrect operation may result when different devices are connected if the input VIL/VIH and the output VOH and VOH levels do not match. Level shifters must be inserted between devices with differing supply voltages, such as those often used in dual power supply systems, to prevent destruction of the devices. Load Capacitance and Output Current If a large load capacitance is connected, the resulting effective short of the outputs may continue for an extended period and lead to fusing of lines. Also, larger charge and discharge currents can cause noise, degrade device performance, and cause incorrect operation. The recommended load capacitance ratings must be observed. Excessive output sink or source currents can lead to the same problems described in the preceding item. Once the allowable power dissipation rating has been met, the recommended current values must be observed as well. Notes on Power Application and Reset There are several aspects that require care when power is first applied, during a reset, and when the reset state is cleared. Refer to the device specifications and design applications to match the product specifications. In this IC, the register contents, pin output states, and pin I/O settings are not guaranteed after power is first applied. Items that are defined by the reset operation or mode setting operations are guaranteed after these operations are performed. After power is first applied to this IC, the application must first perform a reset operation. Pin states and register values that are not defined are subject to change, both due to sample-to-sample variations in the product over the long term, and due to changes in device design from the initial design states. Thermal Design Semiconductor device failure rates are greatly accelerated by inappropriate ambient temperature and power consumption conditions. To assure the highest possible reliability, the thermal design should provide ample margins considering all possible changes in the ambient conditions. No.7350-20/21 LC78684E Notes on PWB Pattern Design In an ideal design, power supply and ground lines will be provided separately for each system to minimize the influence of shared impedances. Power supply and ground lines must be made as wide and as short as possible, and the impedance to high frequencies must be made as low as possible. Decoupling capacitors (consisting of two capacitors: one about 0.01 to 1.0 F and another about 100 to 220 F) should be inserted between each power supply pin and ground. Note, however, that if this capacitance is too large, it may result in latchup problems. Other Notes If you have any questions or if anything is even slightly unclear, please contact your SANYO sales or technical representative during the design phase. This IC is a special-purpose device for use in CD players, and its specifications differ from those of standard logic ICs and other general-purpose products. Also note that, depending on the application, failsafe measures and/or system level debugging of the total system may be required as well. Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 2003. Specifications and information herein are subject to change without notice. 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